LOW POWER PARALLEL PREFIX ADDER

Appled Mechancs and Materals Onlne: 2014-06-18 ISSN: 1662-7482, Vol. 573, pp 194-200 do:10.4028/www.scentfc.net/amm.573.194 2014 Trans Tech Publcatons, Swtzerland LOW POWER PARALLEL PREFIX ADDER P.Kowsalya 1, a*, M.Malath 2,b and Dr.P.Ramanathan 3,c 1&2 M.E (VLSI Desgn) Students,Department of ECE, Info Insttute of Engneerng, Kovlpalayam, Combatore 641107,Tamlnadu, INDIA 3 Professor and Head Department of ECE, Info Insttute of Engneerng, Kovlpalayam, Combatore 641107,Tamlnadu, INDIA a kowsecebe@gmal.com, b malathaucbe@gmal.com c pramanathan_2000@yahoo.com Keywords: Parallel Prefx Adder(PPA),DI technque, CMOS, rent Kung,Kogge Stone, Sklansky, PDP. Abstract. Addton s a fundamental operaton of all Arthmetc and Logc Unts(ALU).The speed of addton operaton decdes the computatonal frequency of ALU. In order to mprove the performance of the bnary adder, the parallel prefx adder are preferred. There are varous Parallel Prefx Adders (PPA) avalable. Ths work focuses on desgnng 8-bt prefx adders such as rent Kung,Kogge Stone and Sklansky adders usng ate Dffuson Input (DI) technque. The performance of these DI based prefx adders are compared wth that of CMOS based prefx adder. DI based prefx adders out performs CMOS based prefx adders n terms of power delay product (PDP). The desgn s mplemented and smulated by DSCH2 and MICROWIND tool.the smulaton result reveal about 31%,40% and 50 % of power savng s attaned and the number of transstors also reduced. Introducton The adder s the most commonly used arthmetc block of the Mcro Processor Unt (MPU) and Dgtal Sgnal Processor (DSP), therefore ts performance and power optmzaton s of utmost mportance. Parallel Prefx Adder (PPA) are very useful n today s world of technology. At the same tme, the power consumpton per chp also ncreases sgnfcantly due to the ncreasng densty of the chp. When hgh operaton speed s requred, the tree structures lke parallel-prefx adders are employed. The Parallel Prefx addton s done n three steps, whch s shown n fg1. 1.The Pre-Processng, 2.Carry raph and 3.Post-Processng. The pre-processng part wll generate the propagate (P) and generate () bts. The fundamental generate and propagate sgnals are used to generate the carry nput for each adder. Two dfferent operators black and gray are beng used here. There are many types of PPA's such as rent Kung, Kogge Stone, Sklansky, Ladner Fsher,Hans Carlson and Knowles. The am of ths paper s to employ the DI based gates n PPA structure and evaluate ther performance. In ths only rent Kung, Kogge Stone adder and Sklansky adder have been consdered. Pre-Calculaton of P, terms Straght forward as n the CLA adder Calculaton of the carres. Ths part s parallelzable to reduce tme Smple adder to generate the sum Prefx graphs can be used to descrbe the structure that performs ths part Straght forward as n the CLA adder Fg 1. Addton procedure usng Parallel Prefx tree structures All rghts reserved. No part of contents of ths paper may be reproduced or transmtted n any form or by any means wthout the wrtten permsson of Trans Tech Publcatons, www.ttp.net. (ID: 130.203.136.75, Pennsylvana State Unversty, Unversty Park, USA-11/05/16,05:57:10)

Appled Mechancs and Materals Vol. 573 195 Lterature survey Ionescu et.al have proposed Systematc Desgn for Integrated Dgtal Crcut Structures.In ths paper the large number of levels n rent Kung Adder (KA) however reduces ts operatonal speed. KA s also power effcent because of ts lowest area, delay wth large number of nput bts [1]. Kogge et.al have proposed an algorthm for Kogge stone adder has both optmal depth and low fan-out[2]. The archtecture [3], saves one logc level mplementaton and reduces the fan-out requrements of the desgn. The adders are Kogge-Stone [4], Sklansky [5] and rent-kung [6] for ther propertes of low logc-level, hgher wrng track; low logc-level, hgh fan-out and hgh logclevel, low fan-out respectvely. Smulaton of tree adder desgned wth Complementary Path Adabatc Logc (CEPAL)was proposed by.nreesha et.al[7] ths paper the mplementaton of the 2-bt Sklansky tree adder structure, desgned wth CEPAL logc, whch has been chosen due to ts ncreased fan-out that results n reduced latency and mproved speed performance[7]. Sklansky J[8] have proposed condtonal-sum addton logc, n ther work the Sklansky tree adder presents a mnmum depth prefx network at the cost of ncreased fan out for certan computaton nodes. In [9], the authors descrbed several Carry Tree Adders mplemented on a Xlnx Spartan3E FPA. It s reported the Kogge Stone carry tree adder provded better delay performance for the hgher order bts. In [10] the Kogge-Stone adder s modfed usng fast carry logc technque. Parallel Prefx Adder Structure The parallel prefx adder employs the 3-stage structure of the CLA adder. The mprovement s n the carry generaton stage whch s the most ntensve one. In every bt () of the two operand block, the two nput sgnals (A and ) are added to the correspondng carry-n sgnal (Carry ) to produce sum output (Sum ) The equaton to produce the sum output s: Sum A carry (1) Computaton of the carry-n sgnals at every bt s the most crtcal and tme consumng operaton. In the carry- look ahead scheme of adders (CLA), the focus s to desgn the carry-n sgnals for an ndvdual bt addtons. Ths s acheved by generatng two sgnals, the generate () and propagate (P) usng the equatons: A (2) P A (3) The carry n sgnal for any adder block s calculated by usng the formula C 1 P Carry (4) Where C must be expanded to calculate C +1 at any level of addton. Parallel Prefx adders compute carry-n at each level of addton by combnng generate and propagate sgnals n a dfferent manner. Two operators namely black and gray are used n parallel prefx trees are shown n fg 2(a), fg 2(b) respectvely., P -1, P -1, P -1, P -1 0, P 0 a) black operator (b) gray operator Fg 2. Operators used n Parallel Prefx trees 0

196 Advancements n Automaton and Control Technologes keep The black operator receves two sets of generate and propagate sgnals (, P ),( -1,P -1 ), computes one set of generate and propagate sgnals ( o, P o ) by the followng equatons: P (5) 0 1 P P p (6) 0 1 The gray operator receves two sets of generate and propagate sgnals (, P ),( -1,P -1 ) computes only one generate sgnal wth the same equaton as n equaton (4). The logc dagram of black operator and gray operator s shown n fg 3(a), fg 3(b) respectvely. Fg 3. Logc dagram of (a) black operator (b) gray operator In ths paper the followng Parallel Prefx adders are consdered for the mplementaton wth the newly redesgned operators: 1. rent Kung Adder(K Adder) 2. Sklansky Adder(SK Adder) 3. Kogge Stone Adder(KS Adder) rent Kung Adder The rent Kung Parallel Prefx Adder has a low fan-out from each prefx cell but has a long crtcal path and s not capable of extremely hgh speed addton. The logc level of ths adder s 2log 2 n-1 and the maxmum fan-out s 2. The large number of levels n rent Kung Adder (KA) however reduces ts operatonal speed. KA s also power effcent because of ts lowest area wth large number of nput bts [11]. The delay of KA s equal to (2*log 2 n)-2 whch s also the number of stages for the o operator. The KA has the area (number of o operators) of (2*n)-2-log 2 n where n s the number of nput bts [12]. The KA s known for ts hgh logc depth wth mnmum area characterstcs [13]. Hgh logc depth here means hgh fan-out characterstcs. The 8-bt rent kung adder s shown n fg 4. 7 6 5 4 3 2 1 0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0 Fg 4. rent Kung adder

Appled Mechancs and Materals Vol. 573 197 Kugge Stone Adder The Kogge Stone adder s a parallel prefx form carry look-ahead adder. It generates the carry sgnals n O(log n) tme, and s wdely consdered the fastest adder desgn possble. It s the common desgn for hgh-performance adders n ndustry. It takes more area to mplement than the rent Kung adder, but has a lower fan-out at each stage, whch ncreases performance. Wrng congeston s often a problem for Kogge Stone adders as well. The tree also contans more P cells; whle ths may not mpact the area f the adder layout s on a regular grd, t wll ncrease power consumpton. In spte of accountng for more area Kogge-Stone adder s generally used for wde adders because t shows the lowest delay among other structures. The 8-bt Kogge Stone adder s shown n fg 5. 7 6 5 4 3 2 1 0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0 Fg 5.Kogge Stone adder Sklansky Adder Sklansky adder belongs to tree adder famly. The dfference between Sklansky adder and other tree adders s prefx network. Compare to other tree adders, Sklansky adder has mnmum logc levels, wrng tracks, but maxmum fan-out. Also, t has largest delay at the same condton. The 8- bt Sklansky adder s shown n fg 6. 7 6 5 4 3 2 1 0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0 Fg 6.Sklansky adder Proposed Work DI Full Adder The fg 7 shows the basc cell of DI. Ths cell s nothng but a standard CMOS nverter, but there are some mportant dfferences [14]such as 1) The DI cell contans three nputs: (common gate nput of nmos and pmos), P (nput to the source/dran of pmos), and N (nput to the source/dran of nmos). 2) ulks of both nmos and pmos are connected to N or P (respectvely), so t can be arbtrarly based at contrast wth a CMOS nverter.

198 Advancements n Automaton and Control Technologes P out N Fg 7.asc cell of DI Table 1. asc functons usng DI cell N P Output Functon 0 1 A A' INVERTER 0 A A' F1 1 A A'+ F2 1 A A+ OR 0 A A AND C A A'+AC MUX ' A A'+'A XOR ' A A+A'' XNOR Varous functons can be mplemented by usng the basc DI cell. MUX desgn s the most complex desgn. In tradtonal CMOS or PTL desgn, the MUX desgn requres 8-12 transstors but n DI technque, the MUX requres only 2 transstors. So the number of transstors can be reduced n a sngle desgn. Many functons can be mplemented effcently by DI wth reduced transstor count. From the table 1, t s observed that usng DI technque AND, OR, Functon1, Functon2, XOR, XNOR can be mplemented more effcently. The unversal gates such as NAND and NOR requre 4 transstors n Statc CMOS desgn. Functon1 and Functon 2 are unversal set for DI, and conssts of only two transstors, compared to NAND and NOR. Advantages of DI over CMOS Technology 1.Consumes Low power 2. Reduces the number of transstors 3. Reduced propagaton delay. 4. Reduced area of dgtal crcut. DI XOR DI XOR,AND and OR gates are shown n fg 8. The XOR requres 4-transstors and MUX functon, AND and OR gates requres only two transstors, ths s mplemented from the Table 1. Vdd P P A out A N Y=A A N Y=A+ Vdd (a) XOR ate (b) AND ate (c) OR ate Fg 8. DI based gates

Appled Mechancs and Materals Vol. 573 199 Results and Dscusson The crcuts were smulated usng 0.25 µm technology. The smulaton results for varous 8-bt PPA usng DI adder and CMOS are tabulated below n Table 2.The number of transstor count also reduced by usng DI that s shown n table 3.In CMOS mplementaton of PPA adders the power has drastcally ncreased due to ncrease n the number of actve devces (transstors).the transstor count s nearly 3 tmes greater than DI mplementaton of PPA. The crcut performance degrades for DI mplementaton of PPA because of threshold voltage problems encountered n pass transstor based desgns. However the PDP for DI based PPA mplementaton outperforms CMOS based PPA adders. Nearly 20% n PDP has been acheved for ent kung adder usng DI when compared CMOS based rent Kung adder. Table 2. Smulaton result of CMOS&DI based PPA CMOS DI PPA Power n mw Delay n ns PDP n 10-12 Ws Power n µw Delay n ns PDP n 10-13 Ws KS 0.827 1.4 1.157 0.233 2.5 0.582 SK 0.508 1.4 0.711 0.204 2.1 0.428 K 0.533 1.1 0.586 0.204 2.0 0.408 Table 3. Transstor Count for CMOS & DI based PPA Number of transstors Number of transstors PPA n CMOS based PPA n DI based PPA KS 538 186 SK 382 138 K 376 136 Concluson In ths paper, we have presented the power characterstcs of three dfferent parallel prefx adders realzed usng CMOS and DI based technque. In all the adders confguratons nvestgated, the DI based PPA exhbt better PDP compared to CMOS based PPA. Among these three 8-bt PPA, the rent Kung adder gves better performance n the characterstc of PDP compared to other parallel prefx adders. Acknowledgments We would lke to thank the Management and Prncpal, Info Insttute of Engneerng, Combatore for provdng the necessary facltes and support.

200 Advancements n Automaton and Control Technologes References [1] V.Ionescu, I. ostan, & L. Ionescu, Systematc Desgn for Integrated Dgtal Crcut Structures, IEEE Journal of Semconductor Conference, 2004, Volume 2, pp 467 470, 2004. [2] Kogge P & Stone H, A Parallel Algorthm For The Effcent Soluton Of A Several Class Of Recurrence Soluton, IEEE trans compu,c-22 (1973)786-793. [3] orgos Dmtrakopoulos and Dmtrc Nkolos, Hgh Speed Parallel Prefx VLSI Lng Adders, IEEE Trans on computers, Vol.54, No.2, Feb 2005. [4] P. M. Kogge and H. S. Stone, A Parallel Algorthm For The Effcent Soluton Of A eneral Class Of Recurrence Equatons, Computers, IEEE Transactons on, vol. C-22, no. 8, pp. 786 793, Aug. 1973. [5] P.. Clem J. Sklansky, Condtonal-sum addton logc, Electronc Computers, IRE Transactons on, vol. EC-9, no. 2, pp. 226 231, June 1960. [6] Informaton. R. rent and H. Kung, A regular layout for parallel adders, Computers, IEEE Transac-tons on, vol. C-31, no. 3, pp. 260 264, March 1982. [7].Nreesha, E.Mahender Reddy & S.Latha, Smulaton of Tree Adder Desgned Wth Complementary Path Adabatc Logc, IOSR Journal of VLSI and Sgnal Processng (IOSR- JVSP) Volume 3, Issue 4 (Nov. Dec. 2013), PP 27-33. [8] SkalanskyJ, Condtonal-Sum addton logc,ire trans Electron compu,ec-9(1960)226-231. [9] FPAs Davd H. K. Hoe, Chrs Martnez and Sr Jyothsna Vundavall, 'Desgn and Characterzaton of Parallel Prefx Adders', IEEE 43rd Southeastern Symposum on system theory, March 2011. [10] Antha R& V agyaveereswaran,hgh Performance Parallel Prefx Adders Wth Fast Carry Chan Logc, Internatonal Journal Of Advanced Research In Engneerng and Technology (Ijaret) volume 3, ssue 2, july-december (2012), pp. 01-10. [11] V. Ionescu, I. ostan, & L. Ionescu,Systematc Desgn for Integrated Dgtal Crcut Structures, IEEE Journal of Semconductor Conference, 2004, Volume 2, pp 467 470, 2004. [12] R. P rent & H. T. Kung, A Regular Layout for Parallel Adders, IEEE Trans. Computers, Vol C-31, pp 260-264, 1982. [13] M. M. Zegler & M. R. Stan, A Unfed Desgn Space for Regular Parallel Prefx Adders, IEEE Journal of Desgn, Automaton and Test n Europe Conference and Exhbton, Volume 2, pp 1386-1387, 2004. [14] Dan Wang, Maofeng Yang, Wu Cheng, Xuguang uan, Zhangmng Zhu, Yntang Yang, 'Novel Low Power Full Adder Cells n 180nm CMOS Technology, IEEE ICIEA 2009.

Advancements n Automaton and Control Technologes 10.4028/www.scentfc.net/AMM.573 Low Power Parallel Prefx Adder 10.4028/www.scentfc.net/AMM.573.194