utca mother board for FMC ADC daughter cards
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1 utca mother board for FMC ADC daughter cards Stefan Korolczuk National Centre for Nuclear Research, Otwock-Świerk, Poland Warsaw, 2011 S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
2 Agenda 1 Introduction 2 Carrier Board 3 Analog mezzanines 4 Board Features 5 Design difficulties 6 Project Status S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
3 Introduction Project Goals: Primary - upgrade of Bunch Arrival Time Monitor electronics (ACB2.1 board) utca platform for direct sampling board (Samer Bou Habib) Basic Features: Support for high accuracy (up to 16 bits) and high speed (up 1GSPS) ADCs utca format - officially chosen for X-FEL and FLASH electronics, Application specific (analog) part on FMC mezzanines Common components (FPGA, power supplies, etc.) are placed on base board Commercial FMC modules can be used Dedicated FMC modules (for BAM) can be designed and reused in future in other projects High performance Virtex-5 FPGA used S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
4 Carrier Board RJ45 and USB Support for double width or two single width FMC AMC.4 compatibility with IPMI support High performance FPGA on board FMC Mezzanine FMC connector FMC connector Power supplies Virtex 5 FXT FPGA DDR2 SO-DIMM Power supplies AMC connector S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
5 Analog mezzanines - FMC FMC - FPGA Mezzanine Card Standard (ANSI/VITA 57.1) Commercial standard (Xilinx involved in standard definition) I/O mezzanine module, works intimately with an FPGA minimize signal latency maximize data throughput. S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
6 Block Diagram S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
7 Board Features Two single or one double size FMC mezzanine support Over 70 differential pairs or 140 single ended signals available for each FMC slot Four Gigabit serial channels per FMC slot Virtex5 FXT70 FPGA with embedded PowerPC440 processor DDR2 SO-DIMM connector IPMI unit Advanced configuration modes with fail-safe configuration memory CF card as a configuration memory, and non-volatile storage for embedded systems Serial port and JTAG over USB Gigabit Ethernet PHY and RJ45 socket for stand-alone operation Watchdog and configuration supervisor implemented in separate small FPGA AMC.4 communication lanes: Gigabit Ethernet PCI Express Two point-2-point links Two M-LVDS links CLKA and CLKB routed to FPGA JTAG S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
8 Difficulties - Schematics Understanding standards and products (a lot of reading...): AMC4 FMC DDR2 Xilinx products Clock generation and distribution circuits FMC and FPGA clock domains FPGA programming S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
9 Difficulties - PCB High speed signal integrity FPGA fanout signals (more than 90% of 1136 FPGA pins usage) DDR2 layout Power Distribution Network Gigabit transceivers Clock distribution network FMC differential lines matched length: two HPC FMC slots differential data lines + clock + Gb lanes 8 clock domains with matched signal lengths (more than 16 diff pairs in one domain) Signals matching is better than 10ps S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
10 Project Status Board has been send to production - expected on VHDL projects for testing following peripherals has been developed: DDR2 memory Gigabit Ethernet FMC connectors (path from connector to first flip-flop) S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
11 Board Layout - Top 16-layers board, FR408 epoxy laminate and pre-preg. S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
12 Component Placement - Top Spartan3AN BPI FLASH PROG FLASH FMC #2 Power Modules Virtex5 CLK GEN AMC CONNECTOR PHY SystemACE USB 2.0 FMC #1 DDR2-SODIMM Power Modules JTAG HDR RJ45 S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
13 Board Layout - Bottom S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
14 Component Placement - Bottom USB IPMI uc CF slot S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
15 Component Height Restriction S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
16 Signal Layers S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
17 The End Thank you for your attention S. Korolczuk (NCBJ) Fast EVM Warsaw / 17
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