Lecture 2: Challenges and Opportunities in System LSI (1) Devices and Circuits

Transcription

1 EE290c Spring 2007, Tues & Thurs 9:30-11:00, 212 Cory UCB Lecture 2: Challenges and Opportunities in System LSI (1) Devices and Circuits Tadahiro Kuroda Visiting MacKay Professor Department of EECS University of California, Berkeley T. Kuroda (1/38)

2 T. Kuroda (2/38) Challenges and Opportunities Discuss challenges and opportunities in 3 levels: 1) Device Level (Physics) 2) Integrated Circuit Level (Electronics) 3) Application and Business Level (Economics)

3 T. Kuroda (3/38) End of CMOS Scaling? ITRS roadmap: solutions are not known (red) 量産年 単位 ゲート長 nm Equivalent Oxide Thickness (EOT) A ゲート空乏化 反転層厚 A 最大ゲートリーク電流 サブスレショルドリーク電流 na/um サブスレショルド特性調節係数 A/cm 2 2.2E E E E E E E E E E 移動度増大係数 飽和速度増大係数 相対性能 Life after CMOS: Imminent or Irrelevant? (DAC 2002, session) Changing Vectors of Moore s Law (IEDM 2002, luncheon) Workshop on Implications of Near-Limit CMOS on Circuits and Applications (ISSCC 2002, workshop) Scaling Limit in a Power Limited Environment, Architecture versus Circuit Design (Symp. VLSI Circuits 2002, panel) For The LAST Time, Who is Going to Solve the POWER Problem! (IEDM 2003, panel)

4 T. Kuroda (4/38) Strategy Shift 2004/10/16 Nikkei Newspaper

5 T. Kuroda (5/38) Multi-Core Montecito (90nm) Intel ISSCC 05 [16.2, 16.7] Dual Cores CELL (90nm SOI) IBM & SONY & Toshiba ISSCC 05 [7.4, 10.2, 20.3, 26.7] Rumbus[28.9] SPE (Synergistic Processing Element) :32bit 8way SIMD

6 T. Kuroda (6/38) Prediction of Lower Limit Pessimistic opinions have been proven wrong time & time again! But, 100 Minimum channel length (um) Prediction Mead Real Life Year of prediction Momose (IEDM 1994) Gate leakage at Tox=1.5nm is accepted under high Ids at L=0.1um -> run into leakage era 2010 Carver Mead & Lynn Conway, Introduction to VLSI Systems (1980) Section 9.8: Quantum mechanical lower limit (tunneling effect will dominate device operation) Thickness such as gate oxide and depletion layer should be larger than several nano-meters.

7 T. Kuroda (7/38) Accelerated CMOS Scaling Research MPU Physical Gate Length (nm) Source: IEDM & Symp. on VLSI Tech ) Competition increases due to ITRS 2) Researchers investigate scaling limit ITRS Year of production L=35nm IEDM 2001, Toshiba L=14nm IEDM 2002, Toshiba L=10nm 2004 Symp. on VLSI Tech., Toshiba L=5nm 2004 Symp. on VLSI Tech., TSMC

8 T. Kuroda (8/38) Degraded Gate Controllability When Tr is not too small, it turns off and saturates. When Tr is too small, it becomes a resistor, since C D becomes comparable to C G. Tr does not turn off, nor saturate. C G G S D C B C D Drain Induced Barrier Lowering (DIBL) Barrier height S Increase Drain voltage Long L D S Increase Drain voltage Short L D

9 T. Kuroda (9/38) Degraded I on / I off Tradeoff: ON / Off (V TH ) Leakage! Ioff (na/u) nm 0.25u tunnel leakage subthreshold leakage Temp (C)

10 T. Kuroda (10/38) New Material Tradeoff: ON / Off (V TH ) high-k (+metal) Leakage! 1) material Strained-Si T. Kuroda, Will SOI ever become a mainstream technology? IEDM 02, panel.

11 Gate Leakage Reduction by High-k & Metal Gate 90nm MOS Transistor Gate oxide thickness is reduced by 2~4A/generation 3A equivalent oxide reduction by using metal gate to eliminate poly-gate depletion layer 50nm Gate ~0.3nm: depleted Gate Leakage Solutions: High-k + Metal Gate T. Kuroda (11/38) issues: mobility, reliability 1.2 nm SiO 2 Silicon substrate 4 layer of SiO 2 molecule Source: Spectrum IEEE,Pat Gelsinger, Intel

12 I ON Increase by Strained Silicon Substrate-Strained Silicon S G NMOS D Ge Process-Induced Strained Silicon S G PMOS D 10-25% higher ON current, 84-97% leakage current reduction or 15% active power reduction. T. Kuroda (12/38) Source: Mark Bohr, Intel

13 New Structure Tradeoff: ON / Off (V TH ) high-k (+metal) Leakage! 1) material 2) structure Strained-Si Ultra Thin Body Double Gate Surrounding Gate T. Kuroda (13/38) T. Kuroda, Will SOI ever become a mainstream technology? IEDM 02, panel.

14 Beyond Conventional CMOS Ultra Thin Body G FinFET D S G D S T Fin ~ (2/3) L g T SOI Substrate ~ (1/3) L g Substrate Lateral CD control by oxidation (not lithography) Gate Source Drain T. Kuroda (14/38) IEDM 2002 (IBM) Source: Intel

15 T. Kuroda (15/38) Multi-Gate CMOS

16 T. Kuroda (16/38) 10nm CMOS (for 2016) Bulk, SiON, 0.9V, metal-gate, elevated S/D (ITRS: SOI, high-k, 0.5V, metal-gate) 9.1. Toshiba : Symp. on VLSI Tech. 2004

17 5nm CMOS (for 2020) T. Kuroda (17/38) TSMC : Symp. on VLSI Tech. 2004

18 T. Kuroda (18/38) Technology Booster Performance Classical Scaling Material high-k metal gate Non-Planer Structure ultra thin body double gate triple gate surrounding gate Mobility Scaling strained Si Year anisotropic surface mobility Ge (thin film on Si wafer) compound semiconductor carbon nanotubes

19 T. Kuroda (19/38) Technology Booster Ioff [µa/µm] HP22 HP32 HP45 HP65 Bulk Strained UTB SG Met. G UTB DG Q. Ballistic Met. Junc. Const. Electric Field Scaling I W on ε t ox ( V V ) GS L TH 2 const. TB improves Ion and mitigates degradation of Ion/Ioff HP90 HP [µa/µm] Ion

20 From Evolutional to Revolutionary 3D integration T. Kuroda (20/38) Carbon nanotube FET

21 Revolutionary Nano Technology ドレイン ゲート 超薄膜チャネル (~2nm) ソース 酸化膜 基板 Molecular devices Single-electron memory (SESO, Hitachi) DNA computing Single-electron logic (SET, Toshiba) T. Kuroda (21/38) Spintronics

22 Challenges and Opportunities Device Level (Physics) Leakage problem shall be solved. Integrated Circuit Level (Electronics) Powerwall (power vs. speed) Variations 1.4 Normalized Frequency % 5X 130nm Normalized Leakage (Isb) T. Kuroda (22/38) Source: S. Borkar, Intel

23 T. Kuroda (23/38) 1000 Power per chip [W] Power Increase by Device Scaling x4 / 3 years x2 x1.4 / 6 / years MPU DSP Year ] Power density : p [W/cm Power dissipation of CMOS chips will steadily be increased as a natural result of device scaling κ 3 MPU DSP κ Scaling variable: κ Hot plate 10

24 T. Kuroda (24/38) Post CMOS ? Bipolar -> NMOS -> CMOS ->? power wall power wall power wall System performance has been improved by integrating more circuits. In the mid-80 s, the increasing level of power dissipation in a chip prompted the industry to shift from bipolar, NMOS technologies to CMOS technology. CMOS delivered better cost performance, since CMOS was a more energy efficient technology and further improved the integration level. We are currently in the same situation as in the mid-80 s. At that time CMOS was on the horizon. However, supplanting of CMOS by yet another more energy efficient technology remains a distant prospect now. Low-power high-speed CMOS technology is becoming an indispensable technology rather than a desirable one. Power wall should be challenged by researchers in multidisciplinary fields.

25 Active Power Will Increase Rapidly Again Power per chip [W] T. Kuroda (25/38) Constant Voltage Scaling x4 / 3 years MPU Constant Field Scaling x2 / 6 years x4 / 3 years x1.1 / 3 years ITRS requirement 1/100 active leakage era tradeoff between speed and power may be difficult DSP published in ISSCC Year

26 MTCMOS Main Cock PLEASE TURN OFF AT THE MAIN When Not In Use T. Kuroda, IEDM 02, panel. T. Kuroda (26/38)

27 VTCMOS PLEASE ADUST PERFORMNACE V TH T. Kuroda, IEDM 02, panel. T. Kuroda (27/38)

28 Please Give Us Controllability on V TH T. Kuroda, IEDM 02, panel. T. Kuroda (28/38)

29 EDA T. Kuroda, IEDM 02, panel. T. Kuroda (29/38)

30 Mostly Regular T. Kuroda, IEDM 02, panel. T. Kuroda (30/38)

31 Ten Tips Tip 1: Optimize and control V DD and V TH. Tip 2: Total power is minimum when P leakage /P active = 30/70. Tip 3: If you don t need to hustle, relax and save power. Tip 4: Utilize surplus timing with multiple V DD s and V TH s. Tip 5: Total power is minimum when V DDL /V DDH =0.7. Tip 6: Two types are sufficient. Tip 7: Adapt to the change with variable V DD and V TH. Tip 8: Two levels are sufficient. Tip 9: Cooperate across various levels of design hierarchy. Tip 10: Right circuit for the right job. T. Kuroda (31/38) T. Kuroda, DAC 03 tutorial

32 T. Kuroda (32/38) Tip 1: Optimize and control V DD and V TH Normalized power Delay P DYNAMIC P SUBTHRESHOLD LEAK P GATE LEAK Normalized delay Drain Induced Barrier Lowering (DIBL) Barrier height S S Increase Drain voltage Long L D D V DD [V] Increase Drain voltage Short L Courtesy: S. Narendra

33 T. Kuroda (33/38) Tip 2: Total power is minimum when P leakage /P active = 30/ Equi-power (solid-lines) κ = P VTH (V) Equi-speed (broken lines) 0.9 κ S = S 1.2 P 1.3 P 1.4 P total P active V 2 DD P leakage P total =30% V DD (V) 70% 30% P leakage 10 s V DD V DD -V TH

34 T. Kuroda (34/38) IBM Power5 P leakage /P active = 30/70 Intel Pentium4 P leak P leak

35 T. Kuroda (35/38) Saving Energy by Working as Slowly as Possible Active E=CV H 2 Sleep Cycle Active E=CV L 2

36 T. Kuroda (36/38) Tip 4: Utilize surplus timing with multiple V DD s and V TH s Supply Voltage Ratio Power Dissipation Ratio { V 1, V 2 } V 2 /V 1 P 2 /P V 1 (V) { V 1, V 2, V 3 } V 2 /V 1 V 3 /V 1 P 3 /P V 1 (V) Tip 4: Utilize surplus timing with multiple V DD s and V TH s. Tip 5: Total power is minimum when V DDL /V DDH =0.7. { V 1, V 2, V 3, V 4 } V 2 /V 1 V 3 /V 1 V 4 /V 1 P 4 /P V 1 (V)

37 T. Kuroda (37/38) Tip 7: Adapt to the change with variable V DD and V TH P limit + - IIR DAC R package P calc Calc Power -> V DD Temp. -> V DD V DD -> f ADC ADC V connector V die Montecito (90nm) 1.5-2X performance 0.8X power of Madison-9M (130nm)

38 T. Kuroda (38/38) Challenges and Opportunities Device Level (Physics) Leakage Problem Integrated Circuit Level (Electronics) Powerwall (power vs. speed) Variations Business Level (Economics) Post PC Applications SoC vs. SiP