Designing, simulation and layout of 6bit full adder in cadence software

Transcription

1 International Research Journal of Applied and Basic Sciences 2014 Available online at ISSN X / Vol, 8 (9): Science Explorer Publications Designing, simulation and layout of 6bit full adder in cadence software Sepideh Fazel 1 1. Tabriz Islamic Azad University Corresponding author fazel.sepideh@gmail.com ABSTRACT: The bit full adders are highly regarded because of their high application in the electrical circuits. There are several factors that contribute to the superiority of one full adder to another one such as high speed, low energy consumption, less area (fewer transistors), low noise and etc. So, far many adder circuits have been proposed that first to design a full adder; a correct choice should be done between option.in the following, some of the famous full adder circuits are introduced briefly and then the best circuit is selected among them in order to design and draw. The time simulation results of circuit schematic and full adder layout are shown finally. Keywords: bit, transistor, full adder INTRODUCTION Collector or adder is a digital circuit that acquires total numbers. In order to collect numbers, collector can be used in BCD mode or in their most applicability mode means the binary numbers.complementary-two method is commonly used in designing a full adder circuit and designed circuit must have a sufficient and high speed, because all of the operations including addition, subtraction, multiplication and division will be calculated by this circuit. full adder is a combination circuit and any combination circuit can be implemented at two levels.the add operation is done faster by lower numbers of levels.although to design the n-bit adder it can be theoretically implemented at two levels,it is not possible practically. Because for designing such a circuit, it is definitely needed to a gate with n- inputs that if n is large number, the gates with high input are actually lower. So, the adder circuit can not be implemented at two levels when n is a large number. Therefore, we have to divide two n-bit numbers in to m-bit groups, sum together and carry the quoted figure of each group to the next group. (Eshragian2001,2002) DESIGNING METHOD Adder selection Figure 1, shows the adder circuit named 'Kang'.This circuit has 52 transistors, as a result it will occupy a large area. Two 'OR' gates,four 'AND' gates, two 'NOR' gates and two 'inverter' have been used to construct this circuit. Figure 2 indicates a adder circuit known as 'Min/Max'.It has 50 transistors and to construct its 'NAND' gates has been only used, (three NAND 2,five NAND 3, one NAND4). Figure 3 indicates a adder circuit 'AOI' that has 40 transistors which is less than two other circuits. Figure 4 presents another kind of kang circuit,this circuit with 28 transistors has the lowest number of transistors So far, we reviewed different adders in terms of circuit structure and the occupied area. In the following, we will deal to functional comparison of above adders and finally we will select the best adder in order to design. (SahebalZamani,; 2008)

2 Figure1.kang adder circuit Figure2.Min/Max adder circuit 1284

3 Figure3.AOI adder circuit Figure4.Second kind of kang adder circuit Functional comparison of adders Table 1 provides a comparison of the mentioned adders. 1285

4 Table1. comparing the adders Kang, AOL, Min /Max ACCORDING TO THE ABOVE TABLE, WE WILL OBTAIN THE FOLLOWING RESULTS Adder circuit in figure 1 has the maximum number of transistors yet the minimum Fan in. It seems that this circuit will be failed at the high logical levels. The circuit in the figure 4 is the best one in terms of transistor number.fan in is high but is not inappropriate as AOT adder. Min/Max adder has the lowest number of logic levels and an acceptable fan in. As the high fan in will increase the transistor number, the area of a circuit with high fan in is more than a circuit with low fan in. According to the mentioned issues, it seems that the circuit in figure 4 is the best selection. DISCUSSION AND CONCLUSION In order to design a 6-bit full adder circuit, first we should design a 1-bit adder circuit. For this purpose, first of all the size of NMOS, PMOS transistors should be selected.so (W/L) p =3/06, (W/L) n =1/5/06 are assumed. Adder circuit schematic in Cadence software is provided in figure 5. Then, we design a symbol for the 1-bit adder circuit by cadence software. Finally, we will obtain a 6-bit adder circuit with putting together of six 1-bit symbol, in a way that C out of every stage enters the C in of the next stage. The schematic of 6bit full adder is shown, as it is evidenced C out of every stage enters the C in of the next stage, except the first and last stage. In the first stage C in is connected to ground and in the last stage C out along S are as output. To reify the circuit performance,adder circuit simulation is done by specter simulator in Cadence software. The results of this simulation (figure 7) represent a true adder performance. (Esteban Tle2012) 1286

5 Figure 5. adder circuit (1-bit). Figure 6.Making adder (6-bit) by the combination of 2-bit adders' symbol. 1287

6 Figure7. The results of time simulation of 1-bit adder Layout of 6-bit adder Ensuring proper operation of the circuit, its layout can be drawn up. In order to minimize noise, VDD and GND are drawn with maximum distance and their metal width is drawn more than metal of other sectors. In order to reduce the area, PMOS transistors on the one side and NMOS transistors on the other side of layout must be plotted.the layout of one bit adder is shown in figure8. ( David Parent, 2007) As it is visible in figure.8, the layout size is approximately 52 22M. All inputs have been entered in the left side of layout, and S, C OUT outputs are taken from the right side and the bottom part of layout, respectively. With putting together of 1-bit adder circuit layout we will reach to 6-bit adder circuit shown in figure.9. David Parent A 6 Bit Multiplier for a DSP SOC Douglas pucknell,eshragian Basic VLSI design Esteban Tlelo-Cuautle and Sheldon X.-D. Tan.2001.,VLSI Design Nill.h.e.vest,Eshragian k Principles of CMOS VLSI Design Sahebazzamani.m,safaee.f,2008,Digital VLSI design Figure8. layout of 1-bit adder circuit REFRENCES 1288