Pareto Points in SRAM Design Using the Sleepy Stack Approach. Abstract
|
|
- Miles Ryan
- 5 years ago
- Views:
Transcription
1 Pareto Points in SRAM Design Using the Sleepy Stack Approach Jun Cheol Park and Vincent J. Mooney III School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA {jcpark, Abstract Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call sleepy stack SRAM. Unlike many other previous approaches, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6T SRAM cell with high-v th transistors, the sleepy stack SRAM cell with 1.5xV th at 110 o C achieves more than 5X leakage power reduction at a cost of 31% delay increase and 113% area increase. Alternatively, by widening wordline pass transistors, the sleepy stack SRAM cell can match the delay of the high-v th 6T SRAM and still achieve 2.5X leakage power reduction at a cost of a 139% area penalty. 1 Introduction Today, power consumption is one of the top concerns of Complementary Metal Oxide Semiconductor (CMOS) circuit design. This is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas including a plethora at the device level and the architectural level. However, due to the significant trade-offs possible in power, delay and area, designers are required to choose appropriate techniques that satisfy application and product needs. Although dynamic power is dominant for technologies at 0.18µ and above, leakage (static) power consumption starts to become a nearly equal partner for technologies below 0.18µ. One of the main contributor to leakage power consumption of a CMOS circuit is subthreshold leakage current, i.e., the source to drain current when the gate voltage is smaller than the transistor threshold voltage. Since subthreshold current increases exponentially as the threshold voltage decreases, deep sub-micron technologies with scaled down threshold voltages will severely suffer from subthreshold leakage power consumption. In addition to subthreshold leakage, another contributor to leakage power is gate-oxide leakage power due to the tunneling current through the gate-oxide insulator. Since gate-oxide thickness will be reduced as the technology decreases, in deep sub-micron technology, gate-oxide leakage power may be comparable to subthreshold leakage power if not handled properly. In this paper, we focus on subthreshold leakage power because we assume other techniques will address gate-oxide leakage; for example, high-k dielectric gate insulators may provide a solution to reduce gate-leakage [1]. Nonetheless, please note that our experimental results measure power consumption of the non-active period which includes both subthreshold and gate-oxide
2 leakage power. Although leakage power consumption is a problem for all CMOS circuits, in this paper we focus on SRAM because SRAM typically occupies large area and transistor count in a System-on-a-Chip (SoC). Furthermore, considering an embedded processor example, SRAM accounts for 60% of area and 90% of the transistor count in Intel XScale [2], and thus may potentially consume large leakage power. In this paper, we propose the sleepy stack SRAM cell design, which is a mixture of changing the circuit structure as well as using high-v th. The sleepy stack technique [3] achieves ultra-large leakage power while maintaining precise logic state in sleep mode, which may be crucial for a product spending the majority of its time in standby mode. Based on the sleepy stack technique, the sleepy stack SRAM cell design takes advantage of ultra-low leakage and state saving. This paper is organized as follows. In Section 2, prior work in low-leakage SRAM design is discussed. In Section 3, our sleepy stack SRAM cell design approach is proposed. In Section 4 and 5, experimental methodology and the results are presented. In Section 6, conclusions are given. 2 Previous work Many ideas have been proposed to reduce leakage power consumption of SRAM because SRAM occupies large area and accounts for large leakage power consumption. One way to reduce leakage power consumption is to exclusively use high-v th transistors in the SRAM. This solution is simple but induces high performance degradation. Azizi et al. observe that in normal programs, most of the bits in a cache are zeros. Therefore, Azizi et al. propose an Asymmetric-Cell Cache; they use high-v th in a subset of transistors in each SRAM cell to save leakage power if the SRAM cell is in the zero state [4]. Although this technique can reduce leakage power at a cost of increased delay overheads, if a benchmark uses mostly non-zero values, leakage power saving is limited. The forced stack technique achieves leakage power reduction by forcing a stack structure [5]. This technique breaks down existing transistors into two transistor and takes an advantage of the stack effect, which reduces leakage power consumption by connecting two or more turned off transistors serially. The forced stack technique can be applied to memory elements such as a register [6] and/or an SRAM cell [7]. However, delay increase may occur due to increased resistance, and the largest leakage savings reported under specific conditions is 90% compared to conventional SRAM in 0.07µ technology [7]. Nii et al. propose Auto-Backgate-Controlled Multi-Threshold CMOS (ABC-MTCMOS) based on the conventional MTCMOS technique, which cuts off logic circuits using high-v th sleep transistors [8]. By using reverse source-body bias during sleep mode, ABC-MTCMOS technique can save leakage power while retaining original state. However, the ABC-MTCMOS technique requires an additional supply voltage throughout the whole SRAM cell array. Further, large electric fields across gates may affect reliability [9]. Similar to MTCMOS, the gated-v dd technique separates a logic block from V dd and Gnd rails using sleep transistors [10]. The gated-v dd technique achieves low-leakage power consumption mainly from the stack effect. However, unlike ABC-MTCMOS, which saves state, the conventional gated-v dd technique loses state in sleep mode (i.e., when the sleep transistors are turned off). To overcome this problem, Powell et al. propose an architectural technique which attempts to put cache lines to sleep which do not currently hold valid data [10]. Although the conventional gated-v dd technique loses the state data when placed in low-power mode, a carefully sized gate transistor may retain the original data. Agarwal et al. study various retaining conditions including temperature, V th, and gate size, and propose Data Retention Gated-Ground Cache (DRG-Cache) [11]. However, since the virtual-gnd node does not hold value 0 firmly, the DRG-Cache design is vulnerable, and even a small 2
3 induced charge may change the stored value [7]. Flautner et al. propose the drowsy cache technique that scales down the supply voltage during drowsy mode [12]. This technique can save leakage power by reducing Drain Induced Barrier Lowering (DIBL) of the short channel devices. The leakage power saving of this technique can be up to 70% [12]. 3 Approach Although previous approaches are effective in some ways, no ideal solution for reducing leakage power consumption is yet known. Therefore, designers choose techniques based upon technology, and associated tradeoffs. In Section 3.1, we introduce our recently proposed low-leakage technique named sleepy stack. In Section 3.2, we then explain our newly proposed sleepy stack SRAM. 3.1 Sleepy stack leakage reduction The sleepy stack technique provides the possibility of choosing a new pareto point considering leakage power and delay. The sleepy stack technique can achieve 1000X leakage power reduction compared to the forced stack technique with some delay and area penalty while saving logic state [3]. on S=0 off S=1 High-Vth on S =1 off S =0 Low-Vth Figure 1: Sleepy stack inverter active mode (left) and sleep mode (right) The sleepy stack technique has a combined structure of the forced stack technique and the sleep transistor technique. This combined structure may achieve smaller delay overhead than the forced stack technique while saving state (unlike other sleep transistor techniques [10, 13], which lose state when in sleep mode). The structure of the sleepy stack approach is shown in Figure 1. The sleepy stack technique divides existing transistors into two transistors each typically with the same width W 1 half the size of the original single transistor s width W 2 (i.e., W 1 = W 2 /2). Then sleep transistors are added in parallel to one of the transistors in each set of two stacked transistors. The divided transistors reduce leakage power using the stack effect while retaining state. The added sleep transistors operate similar to the sleep transistors used in the sleep technique, in which sleep transistors are turned on during active mode and turned off during sleep mode. During active mode, S=0 and S =1 are asserted, and thus all sleep transistors are turned on. Due to the added sleep transistor, the resistance through the activated (i.e., on ) path decreases, and the propagation delay decreases (compared to not adding sleep transistors while leaving the rest of the circuitry the same, i.e., with stacked transistors). During the sleep mode, S=1 and S =0 are asserted, and so both of the sleep transistors are turned off. The stacked transistors in the sleepy stack approach suppress leakage current. One huge advantage of the sleepy stack technique over the forced stack technique is that the sleepy stack technique can use high-v th for both the sleep transistors as well as the transistors in parallel with the sleep transistors [3]. Figure 2 shows results from a chain of 4 inverters, which follows the experimental methodology used 3
4 in [3] while using V dd = 0.8V and varying V th. The results are measured at 25 o C and 110 o C. The delay of the sleepy stack technique with V th =0.4V and V th =0.42V matches the delay of the forced stack technique with original threshold voltage (V th =0.2) at 25 o C and 110 o C, respectively. The sleepy stack technique achieves 215X and 103X leakage reduction at 25 o C and 110 o C, respectively. The sleepy stack technique achieved roughly the same leakage as the sleep transistor technique but with state being saved [3]. (a) Delay (sec) 1.00E E E E E-10 Conventional (25C) Forced stack (25C) Sleepy stack (25C) 7.00E E-10 Conventional (110C) Forced stack (110C) Sleepy stack (110C) 6.00E E E E E E E E E E E Vth 1.00E E+00 (b) Static power (W) Vth 1.00E E E-08 Conventional (25C) Forced stack (25C) Sleepy stack (25C) 1.00E E E-08 Conventional (110C) Forced stack (110C) Sleepy stack (110C) 1.00E E E E E E E E Vth 1.00E E Figure 2: Results from a chain of 4 inverters while varying V th Vth 3.2 Sleepy stack SRAM cell wordline wordline bitline bitline' Figure 3: SRAM cell leakage paths We design an SRAM cell based on the sleepy stack technique. The conventional 6T SRAM cell consists of two coupled inverters and two wordline pass transistors as shown in Figure 3. Since the sleepy stack technique can be applied to each transistor separately, the six transistors can be changed individually. However, to balance current flow (failure of this potentially increases the risk of soft errors [7]), a symmetric design approach is used. 4
5 Table 1: Sleepy stack technique on a SRAM cell Combinations cell leakage reduction bitline leakage reduction Pull-down (PD) sleepy stack medium low Pull-down (PD), wordline (WL) sleepy stack medium high Pull-up (PU), pull-down (PD) sleepy stack high low Pull-up (PU), pull-down (PD), wordline (WL) sleepy stack high high It is very important when applying the sleepy stack technique to consider the various leakage paths in the SRAM cell. The subthreshold leakage current in an SRAM cell is typically categorized into two kinds as shown in Figure 3: (i) cell leakage current that flows from V dd to Gnd internal to the cell and (ii) bitline leakage current that flows from bitline (or bitline ) to Gnd. The bitline leakage occurs due to precharging of bitline and bitline, and the bitline current accounts for 20% of SRAM cell leakage power according to our experiments. Although an SRAM cell is symmetric, the bitline current and bitline current are different according to the stored value. The wordline pass transistor connected to the inverter that holds 1 suppresses leakage current thanks to the stack effect between the wordline pass transistor and the turned off pull-down transistor. However, the wordline pass transistor connected to an SRAM inverter that holds 0 incurs large leakage current. To address the effect of the sleepy stack technique properly, we consider four combinations of the sleepy stack SRAM cell as shown in Table 1. In Table 1, Pull-down sleepy stack means that the sleepy stack technique is only applied to the pull-down transistors of an SRAM cell as indicated in Figure 4. Pull-down, wordline sleepy stack means that the sleepy stack technique is applied to the pull-down transistors as well as wordline transistors. Similarly, Pull-up, pull-down sleepy stack means that the sleepy stack technique is applied to the pull-up transistors and the pull-down transistors of an SRAM cell, and Pull-up, pull-down, wordline sleepy stack means that the sleepy stack technique is applied to all the transistors in an SRAM cell. The pull-down (PD) sleepy stack can suppress some part of the cell leakage. Meanwhile, pull-up (PU) and pulldown (PD) sleepy stack can suppress the majority of the cell leakage. However, without applying the sleepy stack technique to the wordline (WL) transistors, bitline leakage cannot be significantly suppressed. Although lying in the bitline leakage path, the pull-down sleepy stack is not effective to suppress both bitline leakage paths because one of the pull-down sleepy stacks is always on. Therefore, to suppress subthreshold leakage current in a SRAM cell fully, PU, PD and WL sleepy stack need to be considered as shown in Figure 4. The sleepy stack SRAM cell design results in area increase because of the increase of the number of transistors. However, we halve existing transistors and thus the area increase is not directly proportional to the number of transistors. Unlike the conventional 6T SRAM cell, the sleepy stack SRAM cell requires routing of one or two extra wires for the sleep control signal. Figure 5 shows a possible layout of the PU, PD, WL sleepy stack SRAM cell. We only use metal 1 and metal 2 layers for routing because we assume metal layers above metal 2 are reserved for the global routing. Further, the sleepy stack SRAM cell is designed to abut easily. 4 Experimental methodology To evaluate the sleepy stack SRAM cell, we mainly use a simulation based methodology utilizing HSPICE. We compare our technique to (i) using high-v th transistor as direct replacements for low-v th transistors (thus maintaining only 6 transistors in an SRAM cell) and (ii) the forced stack technique [5] because these two techniques are state saving techniques without high risk of soft error [7]. We do not consider Asymmetric-Cell SRAM because 5
6 $! " # % % &! " #! " # % % &! " # Figure 4: Sleepy stack SRAM cell leakage power savings are limited compared to high-v th transistor technique. We first layout SRAM cells of each technique including the conventional 6T SRAM cell. Instead of starting from scratch, we use the CACTI model for the SRAM structure and transistor sizing [14]. We use NCSU Cadence design kit targeting TSMC 0.18µ technology [15]. By scaling down the 0.18µ layout, we obtain 0.07µ technology transistor level HSPICE schematics [16], and we design a 64x64bit SRAM cell array. We estimate area directly from a custom layout using TSMC 0.18µ technology, and we assume the ratios are maintained after scaling the technology down to 0.07µ technology (we are aware this is not exact, hence the word estimate ). We also assume the area of the SRAM cell with high-v th technique is the same as low-v th. This assumption is reasonable because high-v th can be implemented by changing gate oxide thickness, and this almost does not affect area. We estimate dynamic power, static power and read time of the SRAM cell using HSPICE simulation with Berkeley Predictive Technology Model targeting 0.07µ technology [17]. The read time is measured from the time when an enabled wordline reaches 10% of the V dd to the time when either bitline or bitline drops to 90% of the precharged voltage value while the other remains high. This 10% voltage difference between bitline and bitline is typically enough for a sense amplifier to detect the stored cell value [4]. Dynamic power of the SRAM array is measured during the read operation with 2ns of cycle time. Static power of the SRAM cell is measured by turning off sleep transistors if applicable. To avoid leakage power measurement biased by a majority of 1 versus 0 (or vice-versa) values, half of the cells are randomly set to 0, with the remaining half of the cells set to 1. 5 Results We compare the sleepy stack SRAM cell to the conventional 6T SRAM cell, high-v th 6T SRAM cell and the forced stack SRAM cell. For the high-v th technique and the forced stack technique, we consider the same technique combinations applied to the sleepy stack SRAM cell as shown in Table 1 on the previous page. To properly observe the techniques, we compare 13 different cases as shown in Table 2. Case1 is the conventional 6T SRAM cell, which is our base case. Cases 2, 3, 4 and 5 are 6T SRAM cells with the high-v th technique. PD high-v th is the high-v th technique applied only to the pull-down transistors. PD, WL high-v th is the high-v th technique applied to the pull-down transistors as well as the wordline transistors. PU, PD high-v th is the high- V th technique applied to the pull-up and pull-down transistors. PU, PD, WL high-v th is the high-v th technique applied to all the SRAM transistors. Cases 6, 7, 8 and 9 are 6T SRAM cells with the forced stack technique [5]. PD 6
7 Figure 5: Sleepy stack SRAM cell layout stack is the stack technique applied only to the pull-down transistors. PD, WL stack is the stack technique applied to the pull-down transistors as well as the wordline transistors. PU, PD stack is the stack technique applied to the pull-up and pull-down transistors. PU, PD, WL stack is the stack technique applied to all the SRAM transistors. Please note that we do not apply high-v th to the forced stack technique because the forced stack SRAM with high- V th incurs more than 2X delay increase. Cases 10, 11, 12 and 13 are the four sleepy stack SRAM cell approaches as listed in Table 1. For the sleepy stack, high-v th is applied only to the sleep transistors and the transistors parallel to the sleep transistors as shown in Figure Area Table 2: Layout area Technique Height(u) Width(u) Area(u 2 ) Normalized area Case1 Low-Vth Std Case2 PD high-vth Case3 PD, WL high-vth Case4 PU, PD high-vth Case5 PU, PD, WL high-vth Case6 PD stack Case7 PD, WL stack Case8 PU, PD stack Case9 PU, PD, WL stack Case10 PD sleepy stack Case11 PD, WL sleepy stack Case12 PU, PD sleepy stack Case13 PU, PD, WL sleepy stack Table 2 shows the area of each technique. Please note that the SRAM cells can be reduced further by using 7
8 minimum size transistors, but reducting transistor size increases cell read time. Also note, some SRAM cell design, e.g., [18] has 8.2µm 2 cell size using 0.20µ technology, may have smaller size than our design. However, [18] achieves 80% of area reduction over the conventional SRAM cell using a non-conventional CMOS process (while we use a conventioal CMOS process). Furthermore, [18] does not consider area occupied by routing wires while we consider routing wire area to measure more accurate area as shown in Figure 6. Some SRAM cells with the stack technique show smaller area even compared to the base case. For example, the layout of Case8 shown in Figure 7 has smaller area than Case1. Although Case8 has larger width than Case1, the smaller height of Case8 due to reduced transistor width eventually achieves smaller area than Case1. The sleepy stack technique increases area by between 33% and 113%. The added sleep transistors are a bottleneck to reduce the size of the sleepy stack SRAM cells. Further, wiring the sleep control signals makes the design more complicated as shown inn Figure 5. Figure 6: Conventional 6-T SRAM cell layout Figure 7: Forced stack SRAM cell layout 8
9 5.2 Cell read time Table 3: Cell read time Delay (sec) Normalized delay Technique 25 C 110 C 25 C 110 C 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth Low-Vth Std 1.04E E PD high-vth 1.06E E E E PD, WL high-vth 1.16E E E E PU, PD high-vth 1.06E E E E PU, PD, WL high-vth 1.15E E E E PD stack 1.42E E PD, WL stack 1.71E E PU, PD stack 1.40E E PU, PD, WL stack 1.77E E PD sleepy stack 1.33E E E E PD, WL sleepy stack 1.52E E E E PU, PD sleepy stack 1.33E E E E PU, PD, WL sleepy stack 1.51E E E E Although SRAM cell read time changes slightly as temperature changes, the impact of temperature on the cell read time is quite small. However, the impact of threshold voltage is large. We apply 1.5xV th and 2xV th for the high-v th technique and the sleepy stack technique. As shown in Table 3, the delay penalty of the forced stack technique is between 35% and 70% compared to the standard 6T cell. This is one of the primary reasons that the stack technique cannot use high-v th without incurring dramatic delay increases (e.g., 2X or more delay penalty is observed using either 1.5xV th or 2xV th ). Among the three low-leakage techniques, the sleepy stack technique is the second best in terms of delay. Since we are aware that area and delay are critical factors when designing SRAM, we will explore area and delay impact using tradeoffs in Section 5.4. However, let us first discuss leakage reduction (i.e., without yet focusing on tradeoffs, which will be the focus of Section 5.4). 5.3 Leakage power We measure leakage power while changing threshold voltage and temperature because the impact of threshold voltage and temperature on leakage power is significant. Table 4 shows normalized leakage power consumption with two high-v th values, 1.5xV th and 2xV th, and two temperatures, 25 o C and 110 o C, where Case1 and the cases using the stack technique (Cases 6, 7, 8 and 9) are not affected by changing V th because these use only low-v th. Table 4: Leakage power Leakage power (W) Normalized leakage power Technique 25 C 110 C 25 C 110 C 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth Case1 Low-Vth Std 9.71E E Case2 PD high-vth 5.31E E E E Case3 PD, WL high-vth 2.01E E E E Case4 PU, PD high-vth 3.68E E E E Case5 PU, PD, WL high-vth 3.79E E E E Case6 PD stack 5.38E E Case7 PD, WL stack 2.15E E Case8 PU, PD stack 3.75E E Case9 PU, PD, WL stack 5.39E E Case10 PD sleepy stack 5.18E E E E Case11 PD, WL sleepy stack 1.80E E E E Case12 PU, PD sleepy stack 3.54E E E E Case13 PU, PD, WL sleepy stack 1.62E E E E
10 5.3.1 Results at 25 o C Our results at 25 o C show that Case5 is the best with 2xV th and Case13 is the best with 1.5xV th. Specially, at 1.5xV th, Case5 and Case13 achieve 25X and 60X leakage reduction over Case1, respectively. However, the leakage reduction comes with delay increase. The delay penalty is 11% and 45%, respectively, compared to Case Results at 110 o C Absolute power consumption numbers at 110 o C show more than 10X increase of leakage power consumption compared to the results at 25 o C. This could be a serious problem for SRAM because SRAM often resides next to a microprocessor whose temperature is high. At 110 o C, the sleepy stack technique shows the best result in both 1.5xV th and 2xV th even compared to the high-v th technique. The leakage performance degradation under high temperature is very noticeable with the high-v th technique and the forced stack technique. For example, at 25 o C the high-v th technique with 1.5xV th (Case5) and the forced stack technique (Case9) show around 96% leakage reduction. However, at 110 o C the same techniques show around 91% of leakage power reduction compared to Case1. Only the sleepy stack technique achieves superior leakage power reduction; after increasing temperature, the sleepy stack SRAM shows 5.1X and 4.8X reductions compared to Case5 and Case9, respectivley, with 1.5xV th. When the low-leakage techniques are applied only to the pull-down transistors, leakage power reduction is at most 47% (1.5xV th 110 o C) because bitline leakage cannot be suppressed. However, if the techniques are applied to the wordline, additional leakage reduction is achieved. The results are similar in case of techniques only applied to pull-up and pull-down. Without handling bitline leakage properly, 65% or more leakage power reduction cannot be achieved in our simulation result. Although bitline leakage is smaller than cell leakage, without bitline leakage reduction, the overall leakage power reduction is limited. 5.4 Tradeoffs in low-leakage techniques Although the sleepy stack technique shows superior results in terms of leakage power, we need to explore area, delay and power together because the sleepy stack technique comes with non-negligible area and delay penalties. To be compared with the high-v th technique at the same delay, the wordline and pull-down transistors of the sleepy stack are increased until the sleepy stack delay is approximately equal to the delay of the 6T high-v th case. The results are shown in Table 5 in which * means a technique with adjusted transistor width. To enhance readability of tradeoffs, the table is sorted by leakage power. Although we compared four different simulation conditions, we take the condition with 1.5xV th at 110 o C as an important representative technology point at which to compare the trade-offs between techniques. We choose 110 o C because generally SRAM operates at a high temperature and also because high temperature is the worst case. Furthermore, 1.5xV th is chosen because the delay with 1.5xV th is 10% less than with 2xV th (the relative areas are approximately equal). In Table 5, we observe six pareto points, which are in shaded rows, considering three variables of leakage, delay, and area. Case13 shows the lowest possible leakage, at least 5X smaller than the leakage of any of the prior approaches considered; however, there is a corresponding delay and area penalty. Case13* shows the same delay (within 0.2%) as Case5 and is approximately 25% faster than Case13; furthermore, Case13* shows a 2.5X leakage reduction over Case5. In addition, Case13* is only 11.2% slower than the fastest pareto point, Case1, yet has 29X less power consumption than Case1. In short, this paper presents new, previously unknown pareto points at the low-leakage end of the spectrum. 10
11 Table 5: Tradeoffs (1.5xV th, 110 o C) Technique Static (W) Delay (sec) Area (u 2 ) Normalized leakage Normalized delay Normalized area Case1 Low-Vth Std 1.25E E Case2 PD high-vth 7.16E E Case3 PD, WL high-vth 3.20E E Case4 PU, PD high-vth 5.04E E Case5 PU, PD, WL high-vth 1.07E E Case6 PD stack 7.07E E Case7 PD, WL stack 3.20E E Case8 PU, PD stack 4.95E E Case9 PU, PD, WL stack 1.04E E Case10 PD sleepy stack 6.62E E Case11 PD, WL sleepy stack 2.45E E Case12 PU, PD sleepy stack 4.43E E Case13 PU, PD, WL sleepy stack 2.09E E Case10* PD sleepy stack* 6.74E E Case11* PD, WL sleepy stack* 2.72E E Case12* PU, PD sleepy stack* 4.53E E Case13* PU, PD, WL sleepy stack* 4.31E E Active power Table 6: Active power Active power (W) Normalized active power Technique 25 C 110 C 25 C 110 C 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth 1xVth 1.5xVth 2xVth Case1 Low-Vth Std 8.19E E Case2 PD high-vth 7.67E E E E Case3 PD, WL high-vth 7.02E E E E Case4 PU, PD high-vth 7.60E E E E Case5 PU, PD, WL high-vth 6.86E E E E Case6 PD stack 7.58E E Case7 PD, WL stack 5.45E E Case8 PU, PD stack 7.41E E Case9 PU, PD, WL stack 5.22E E Case10 PD sleepy stack 8.03E E E E Case11 PD, WL sleepy stack 6.32E E E E Case12 PU, PD sleepy stack 7.87E E E E Case13 PU, PD, WL sleepy stack 5.89E E E E Table 6 shows power consumption during read operations. The active power consumption includes dynamic power used to charge and discharge SRAM cells plus leakage power consumption. At 25 o C leakage power is less than 20% of the active power in case of the standard low-v th SRAM cell in 0.07µ technology according to the modeling we use from [17]. However, leakage power increases 10X as the temperature changes to 110 o C although active power increases 3X. At 110 o C, leakage power is more than half of the active power from our simulation results. Therefore, without an effective leakage power reduction technique, total power consumption even in active mode is affected significantly. 5.6 Static noise margin Changing the SRAM cell structure may change the static noise immunity of the SRAM cell. Thus, we measure the static noise margin (SNM) of the sleepy stack SRAM cell and the conventional 6T SRAM cell using the butterfly plots in Figure 8. The SNM is defined by the size of the maximum nested square in a butterfly plot. The SNM of the sleepy stack SRAM cell is measured twice in active mode and sleep mode, and results are shown in Table 7. The 11
12 1 Conventional SRM cell Sleepy stack SRAM cell (active mode) Sleepy stack SRAM cell (sleep mode) Volts Volts Figure 8: Static noise margin analysis Table 7: Staci noise margin Technique Static noise margin (V) Active mode Sleep mode Case1 Low-Vth Std Case10 PD sleepy stack Case11 PD, WL sleepy stack Case12 PU, PD sleepy stack Case13 PU, PD, WL sleepy stack SNM of the sleepy stack SRAM cell in active mode is 0.30V and almost similar to the SNM of the conventional SRAM cell. In sleep mode, the SNM of the sleepy stack SRAM cell is improved to 0.38V. Therefore, the sleepy stack SRAM cell appears to be similar to a conventional SRAM cell in static noise immunity. Although we did not perform a process variation analysis, we expect that the high SNM of the sleepy stack SRAM cell makes the technique as immune to process variations as a conventional SRAM cell. 6 Conclusions In this paper we have presented and evaluated our newly proposed sleepy stack SRAM. For example, the sleepy stack SRAM provides the largest leakage savings 416X among all alternatives considered. Specifically, compared to a standard SRAM cell Case1 Table 4 shows that at 110 o C and 2xV th, Case13 reduces leakage by 416X as compared to Case1; unfortunately, this 416X reduction comes as a cost of a delay increase of 50.4% and an area penalty of 113%. Resizing the sleepy stack SRAM can reduce delay significantly at a cost of less leakage savings; specifically, Case13* is an interesting pareto point as discussed in Section 5.4. We believe that this paper presents a dramatic development because our sleepy stack SRAM seems to provide, in general, the lowest leakage pareto points of any VLSI design style known to the authors. Given the nontrivial area penalty (e.g., up to 138.9% for Case13* in Table 5), perhaps sleepy stack SRAM would be most appropriate for a small SRAM intended to store minimal standby data for an embedded system spending significant time in standby mode; for such a small SRAM (e.g., 16KB), the area penalty may be acceptable given system-level standby power 12
13 requirements. If absolute minimum leakage power is extremely critical, then perhaps specific target embedded systems could use sleepy stack SRAM more widely. For future work, we will model the dynamic and leakage power consumption and delay of the rest of SRAM (address decoder, sense amplifier, precharging logic and column MUX) and evaluate techniques for architectural level SRAM power reduction. References [1] N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan, Leakage Current: Moore s Law Meets Static Power, IEEE Computer, vol. 36, pp , December [2] L. Clark, E. Hoffman, J. Miller, M. Biyani, L. Luyun, S. Strazdus, M. Morrow, K. Velarde, and M. Yarch, An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications, IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp , November [3] J. Park, V. J. Mooney, and P. Pfeiffenberger, Sleepy Stack Reduction in Leakage Power, Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp , September [4] N. Azizi, A. Moshovos, and F. Najm, Low-Leakage Asymmetric-Cell SRAM, Proceedings of the International Symposium on Low Power Electronics and Design, pp , August [5] S. Narendra, V. D. S. Borkar, D. Antoniadis, and A. Chandrakasan, Scaling of Stack Effect and its Application for Leakage Reduction, Proceedings of the International Symposium on Low Power Electronics and Design, pp , August [6] S. Tang, S. Hsu, Y. Ye, J. Tschanz, D. Somasekhar, S. Narendra, S.-L. Lu, R. Krishnamurthy, and V. De, Scaling of Stack Effect and its Application for Leakage Reduction, Symposium on VLSI Circuits Digest of Technical Papers, pp , June [7] V. Degalahal, N. Vijaykrishnan, and M. Irwin, Analyzing soft errors in leakage optimized SRAM design, IEEE International Conference on VLSI Design, pp , January [8] K. Nii, H. Makino, Y. Tujihashi, C. Morishima, Y. Hayakawa, H. Nunogami, T. Arakawa, and H. Hamano, A Low Power SRAM Using Auto-Backgate-Controlled MT-CMOS, Proceedings of the International Symposium on Low Power Electronics and Design, pp , August [9] H. Hanson, M. S. Hrishikesh, V. Agarwal, S. W. Keckler, and D. Burger, Static energy reduction techniques for microprocessor caches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp , June [10] M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-submicron Cache Memories, Proceedings of the International Symposium on Low Power Electronics and Design, pp , July [11] A. Agarwal, L. Hai, and K. Roy, DRG-Cache: A Data Retention Gated-Ground Cache for Low Power, Proceedings of the Design Automation Conference, pp , June [12] K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, Drowsy Caches: Simple Techniques for Reducing Leakage Power, Proceedings of the International Symposium on Computer Architecture, pp , May [13] K.-S. Min, H. Kawaguchi, and T. Sakurai, Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self- Adaptive Voltage Level Controller: An Alternative to Clock-gating Scheme in Leakage Dominant Era, IEEE International Solid-State Circuits Conference, vol. 1, pp , February [14] S. Wilton and N. Jouppi, An Enhanced Access and Cycle Time Model for On-Chip Caches. [Online]. Available [15] NC State University Cadence Tool Information. [Online]. Available 13
14 [16] P. Pfeiffenberger, J. Park, and V. Mooney, Some Layouts Using the Sleepy Stack Approach, Georgia Institute of Technology, Tech. Rep. GIT-CC-04-05, June [Online]. Available: [17] Berkeley Predictive Technology Model (BPTM). [Online]. Available ptm/. [18] F. Ootsuka, M. Nakamura, T. Miyake, S. Iwahashi, Y. Ohira, T. Tamaru, K. Kikushima, and K. Yamaguchi, A Novel 0.20um Full CMOS SRAM cell Using Stacked Cross Couple with Enhanced Soft Error Immunity, IEEE International Electron Devices Meeting, pp , December
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Pareto Points in SRAM Design Using the Sleepy Stack Approach Jun Cheol Park and Vincent J. Mooney III School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA 30332 {jcpark,
More informationPareto Points in SRAM Design Using the Sleepy Stack Approach
Pareto Points in SRAM Design Using the Sleepy Stack Approach Jun Cheol Park^ and Vincent J. Mooney III* *Associate Director, ^Center for Research on Embedded Systems and Technology (CREST), http://www.crest.gatech.edu
More informationSleepy stack: a New Approach to Low Power VLSI Logic and Memory
Sleepy stack: a New Approach to Low Power VLSI Logic and Memory Ph.D. Dissertation Defense by Jun Cheol Park Advisor: Vincent J. Mooney III School of Electrical and Computer Engineering Georgia Institute
More informationAustralian Journal of Basic and Applied Sciences. Performance Analysis of Different Types of Adder Using 3-Transistor XOR Gate
ISSN:1991-8178 Australian Journal of Basic and Applied Sciences Journal home page: www.ajbasweb.com Performance Analysis of Different Types of Adder Using 3-Transistor XOR Gate Lourdy Nivethitha, V. and
More informationDesign of 16-Bit Adder Structures - Performance Comparison
Volume 118 No. 24 2018 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ Design of 16-Bit Adder Structures - Performance Comparison Padma Balaji R D, Tarun
More informationDesign of a High Speed Adder
Design of a High Speed Adder Aritra Mitra 1, Bhavesh Sharma 2, Nilesh Didwania 3 and Amit Bakshi 4 Aritra.mitra000@gmail.com, Abakshi.ece@gmail.com Abstract In this paper we have compared different addition
More informationDesign of 64-bit hybrid carry select adder using CMOS 32nm Technology
Design of 64-bit hybrid carry select adder using CMOS 32nm Technology Gurdeep Kaur 1, Candy Goyal 2, Kuldeep Singh 3 1 M.Tech Student, Yadwindra College of Engineering, Talwandi Sabo, India 2Assistant
More informationDesign of High Speed Vedic Multiplier Using Carry Select Adder with Brent Kung Adder
Design of High Speed Vedic Multiplier Using Carry Select Adder with Brent Kung Adder Kathi Anoosha M.Tech(VLSI&ES), AVN Institute of Engineering and Technology. Sasi Kiran, M.Tech Assistant Professor,
More informationDesigning, simulation and layout of 6bit full adder in cadence software
International Research Journal of Applied and Basic Sciences 2014 Available online at www.irjabs.com ISSN 2251-838X / Vol, 8 (9): 1283-1288 Science Explorer Publications Designing, simulation and layout
More informationDesign of 32 bit Parallel Prefix Adders
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. Volume 6, Issue 1 (May. - Jun. 2013), PP 01-06 Design of 32 bit Parallel Prefix Adders P.Chaitanya
More informationImplementation of 16-Bit Area Efficient Ling Carry Select Adder
Implementation of 16-Bit Area Efficient Ling Carry Select Adder P.Nithin 1, PG Student, SRKR Engineering College, Bhimavaram, India. N.Udaya kumar 2, Professor, SRKR Engineering College, Bhimavaram, India.
More informationREVIEW OF CARRY SELECT ADDER BY USING BRENT KUNG ADDER
REVIEW OF CARRY SELECT BY USING BRENT KUNG Pappu P Potdukhe 1, Vishal D Jaiswal 2 Abstract In order to perform the addition of two numbers adder is used Adder also form the integral part of ALU Besides
More informationDesign of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder Dr.K.Srinivasulu Professor, Dept of ECE, Malla Reddy Collage of Engineering. Abstract: The binary addition is the basic arithmetic
More informationA Novel Approach For Error Detection And Correction Using Prefix-Adders
A Novel Approach For Error Detection And Correction Using Prefix-Adders B. Naga Jyothi* 1, K.S.N.Murthy 2, K.Srinivasarao 3 *1 PG Student Department of ECE, K.L. University Green fields-522502, AP, India
More informationINTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET)
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET) International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 ISSN 0976-6480 (Print) ISSN
More informationDesign of Carry Select Adder with Binary Excess Converter and Brent Kung Adder Using Verilog HDL
Design of Carry Select Adder with Binary Excess Converter and Brent Kung Adder Using Verilog HDL Andoju Naveen Kumar M.Tech (VLSI & Embedded System), Siddhartha Institute of Engineering and Technology.
More informationComparative Analysis of Adders Parallel-Prefix Adder for Their Area, Delay and Power Consumption
2018 IJSRST Volume 4 Issue 5 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Comparative Analysis of Adders Parallel-Prefix Adder for Their Area, Delay and Power Consumption
More informationImplementation and Estimation of Delay, Power and Area for Parallel Prefix Adders
International Journal for Modern Trends in Science and Technology Volume: 02, Issue No: 11, November 2016 http://www.ijmtst.com ISSN: 2455-3778 Implementation and Estimation of Delay, Power and Area for
More informationDesign and Estimation of delay, power and area for Parallel prefix adders
Design and Estimation of delay, power and area for Parallel prefix adders Divya Tejaswi Pirati P.G. Scholar, Department of Electronics & Communication Engineering, VRS &YRN College of Engineering & Technology,
More information16-BIT CARRY SELECT ADDER. Anushree Garg B.Tech Scholar, JVW, University, Rajasthan, India
International Journal of Engineering Science and Generic Research (IJESAR) Available Online at www.ijesar.in Volume 2; Issue 3; May-June-2016; Page No. 19-24 16-BIT CARRY SELECT ADDER Anushree Garg B.Tech
More informationDesign of Modified Low Power and High Speed Carry Select Adder Using Brent Kung Adder
Journal From the SelectedWorks of Kirat Pal Singh August, 2016 Design of Modified Low Power and High Speed Carry Select Adder Using Brent Kung Adder Amala Maria Alex, Mangalam college of Engineering, Kottayam,
More informationLecture 2: Challenges and Opportunities in System LSI (1) Devices and Circuits
EE290c Spring 2007, Tues & Thurs 9:30-11:00, 212 Cory UCB Lecture 2: Challenges and Opportunities in System LSI (1) Devices and Circuits Tadahiro Kuroda Visiting MacKay Professor Department of EECS University
More informationComparison of Parallel Prefix Adders Performance in an FPGA
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 3, Issue 6 (September 2012), PP. 62-67 Comparison of Parallel Prefix Adders Performance
More informationDesign of Carry Select Adder Using Brent Kung Adder and BEC Adder
Design of Carry Select Adder Using Brent Kung Adder and BEC Adder Habeebunnisa Begum, B.E M.Tech (VLSI & Embedded Systems), Adusumilli Vijaya Institute of Technology and Research Centre. Abstract: The
More informationDEVISE AND INFERENCE OF DELAY, POWER AND AREA FOR ANALOGOUS PREFIX ADDERS
DEVISE AND INFERENCE OF DELAY, POWER AND AREA FOR ANALOGOUS PREFIX ADDERS P.S.N Bhaskar 1, K.M.Manjunath 2 1,2 Department of ECE, Alwardas Group, Andhra University, (India) ABSTRACT Analogous Prefix Adders
More informationCat Swarm Optimization
Cat Swarm Optimization Shu-Chuan Chu 1, Pei-wei Tsai 2, and Jeng-Shyang Pan 2 1 Department of Information Management, Cheng Shiu University 2 Department of Electronic Engineering, National Kaohsiung University
More informationImproving RLP Performance by Differential Treatment of Frames
Improving RLP Performance by Differential Treatment of Frames Mainak Chatterjee Department of Electrical and Computer Engineering University of Central Florida Orlando, FL 386-4 Email: mainak@cs.ucf.edu
More informationA COMPREHENSIVE SURVEY ON VARIOUS ADDERS AND ITS COMPACTION RESULT
Volume 118 No. 22 2018, 1021-1029 ISSN: 1314-3395 (on-line version) url: http://acadpubl.eu/hub ijpam.eu A COMPREHENSIVE SURVEY ON VARIOUS ADDERS AND ITS COMPACTION RESULT 1 Kaarthik K, 2 T.Jayanthi, 3
More informationPixie-7P. Battery Connector Pixie-7P Fuse* Motor. 2.2 Attaching the Motor Leads. 1.0 Features of the Pixie-7P: Pixie-7P Batt Motor
1.0 Features of the Pixie-7P: Microprocessor controlled Low Resistance (.007 ohms) High rate (2800 Hz) switching (PWM) Up to 7 Amps continuous current (with proper air flow) High Output (1.2amp) Battery
More informationMGL Avionics EFIS G2 and iefis. Guide to using the MGL RDAC CAN interface with the UL Power engines
MGL Avionics EFIS G2 and iefis Guide to using the MGL RDAC CAN interface with the UL Power engines General The RDAC CAN interface forms the bridge between the UL Power ECU and an MGL Avionics G2 EFIS system
More informationFAQ (Frequently Asked Questions)
File: FAQ-FCI-Updated-12-21-12 Page: 1 of 11 Table of Contents Pg(s) I. Benefits of using FCI s... 1 II. Installation... 2-5 III. AccQTrip for OLM & UCM Models... 5 IV. Adaptive trip Logic for 1547 & 1548
More informationDESIGN AND SIMULATION OF 4-BIT ADDERS USING LT-SPICE
DESIGN AND SIMULATION OF 4-BIT ADDERS USING LT-SPICE Kumari Amrita 1, Avantika Kumari 2 1,2 B.Tech-M.Tech Student VLSI, Department of Electronics and Communication, Jayoti Vidyapeeth Women's University,
More informationDesign of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder Pallavi Saxena Assistant Professor, Department of ECE Kautilya Institute of Technology and Engineering Jaipur, India pallavisaxena.ei@gmail.m
More informationFPGA-based Emotional Behavior Design for Pet Robot
FPGA-based Emotional Behavior Design for Pet Robot Chi-Tai Cheng, Shih-An Li, Yu-Ting Yang, and Ching-Chang Wong Department of Electrical Engineering, Tamkang University 151, Ying-Chuan Road, Tamsui, Taipei
More informationPetSpy Premium Dog Training Collar, Models M919-1/M919-2
PetSpy Premium Dog Training Collar, Models M919-1/M919-2 What is in the Package: M919-1/M919-2 Remote Transmitter Receiver Collar / E-Collar Radio Frequency: 900 Mhz Built-in Batteries information: Transmitter:
More information5 State of the Turtles
CHALLENGE 5 State of the Turtles In the previous Challenges, you altered several turtle properties (e.g., heading, color, etc.). These properties, called turtle variables or states, allow the turtles to
More informationA Flexible natural gas membrane Reformer for m- CHP applications FERRET
A Flexible natural gas membrane Reformer for m- CHP applications FERRET This project is supported by the European Union s Seventh Framework Programme (FP7/2007-2013) for the Fuel Cells and Hydrogen Joint
More informationA Column Generation Algorithm to Solve a Synchronized Log-Truck Scheduling Problem
A Column Generation Algorithm to Solve a Synchronized Log-Truck Scheduling Problem Odysseus 2012 Greg Rix 12 Louis-Martin Rousseau 12 Gilles Pesant 13 1 Interuniversity Research Centre on Enterprise Networks,
More informationREPORT ON SCOTTISH EID TRIALS
REPORT ON SCOTTISH EID TRIALS PREPARED FOR: SEERAD PREPARED BY: SAOS Ltd Rural Centre West Mains Ingliston, EH28 8NZ January 2007 CONTENTS 1. Introduction 2 Page 2. Trial Objectives. 2 3. Methodology..
More informationPetSpy Advanced Dog Training System, Model M86N
PetSpy Advanced Dog Training System, Model M86N What is in the Package: PetSpy Advanced Dog Training System: Remote Transmitter Receiver Collar Frequency: 433.825Mhz Transmitter: 3.7V 500mA LiPo Receiver:
More informationBroiler Management for Birds Grown to Low Kill Weights ( lb / kg)
Broiler Management for Birds Grown to Low Kill Weights (3.3-4.0 lb / 1.5-1.8 kg) April 2008 Michael Garden, Regional Technical Manager Turkey, Middle East & Africa, Aviagen Robin Singleton, Technical Service
More informationSmart bark control collar BC-2. User manual
Smart bark control collar BC-2 User manual Important: Read this manual carefully before using the Smart Bark Control Collar for the safety of you and your dog. Welcome to the Family! Thank you for choosing
More informationApplicability of Earn Value Management in Sri Lankan Construction Projects
Applicability of Earn Value Management in Sri Lankan Construction Projects W.M.T Nimashanie 1 and A.A.D.A.J Perera 2 1 National Water Supply and Drainage Board Regional Support Centre (W-S) Mount Lavinia
More informationFemale Persistency Post-Peak - Managing Fertility and Production
May 2013 Female Persistency Post-Peak - Managing Fertility and Production Michael Longley, Global Technical Transfer Manager Summary Introduction Chick numbers are most often reduced during the period
More informationFemale Persistency Post-Peak - Managing Fertility and Production
Female Persistency Post-Peak - Managing Fertility and Production Michael Longley, Global Technical Transfer Manager May 2013 SUMMARY Introduction Chick numbers are most often reduced during the period
More informationEffective Vaccine Management Initiative
Effective Vaccine Management Initiative Background Version v1.7 Sep.2010 Effective Vaccine Management Initiative EVM setting a standard for the vaccine supply chain Contents 1. Background...3 2. VMA and
More informationBreeder Cobb 700. The Cobb 700 has been introduced to meet the. Ten years of research to develop Cobb 700. Breeder Performance
Product Profile Breeder Ten years of research to develop The has been introduced to meet the increasing demand not just for more breast meat, but for breast meat produced at the lowest cost. The need to
More informationA Flexible natural gas membrane Reformer for m- CHP applications FERRET
A Flexible natural gas membrane Reformer for m- CHP applications FERRET This project is supported by the European Union s Seventh Framework Programme (FP7/2007-2013) for the Fuel Cells and Hydrogen Joint
More informationS Fault Indicators. S.T.A.R. Type CR Faulted Circuit Indicator Installation Instructions. Contents PRODUCT INFORMATION
Fault Indicators S.T.A.R. Type CR Faulted Circuit Indicator Installation Instructions Service Information S320-75-1 Contents Product Information..........................1 Safety Information............................2
More informationUser s Guide. High Performance Linear Products SLOU119
User s Guide December 2001 High Performance Linear Products SLOU119 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
More information328 A Russell Senate Office Building United States Senate
July 3, 2012 The Honorable Debbie Stabenow The Honorable Herb Kohl Chair Chair Committee on Agriculture Subcommittee on Agriculture Committee on Appropriations 328 A Russell Senate Office Building S-128
More informationIEEE Std 592 Test Program using Current Cable Accessories and Installation Practices
IEEE Std 592 Test Program using Current Cable Accessories and Installation Practices Thomas J. Parker GTRC 1 Notice a. The material contained herein is, to our knowledge, accurate and reliable at the date
More informationGARNET STATIC SHOCK BARK COLLAR
GARNET STATIC SHOCK BARK COLLAR Congratulations on buying this Our K9 Bark Collar, if for any reason you are not 100% completely satisfied with your Bark Collar, please contact me immediately so that I
More informationFrequently Asked Questions
Frequently Asked Questions INNOTEK FAQ What is a Pet Containment System? Innotek Containment Systems create a hidden boundary for dogs. The receiver on the dog's collar will sound a warning tone as the
More informationFPGA Implementation of Efficient 16-Bit Parallel Prefix Kogge Stone Architecture for Convolution Applications Geetha.B 1 Ramachandra.A.
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 05, 2014 ISSN (online): 2321-0613 FPGA Implementation of Efficient 16-Bit Parallel Prefix Kogge Stone Architecture for
More informationIQ Range. Electrical Data 3-Phase Power Supplies. Keeping the World Flowing
IQ Range Electrical Data 3-Phase Power Supplies Keeping the World Flowing Contents Section Page Introduction 3 50 Hz 380 V 5 0 V 6 415 V 7 4 V 8 500 V 9 6 V 60 Hz 8 V 11 2 V 0 V 13 4 V 14 460 V 15 480
More informationComparative Evaluation of Online and Paper & Pencil Forms for the Iowa Assessments ITP Research Series
Comparative Evaluation of Online and Paper & Pencil Forms for the Iowa Assessments ITP Research Series Catherine J. Welch Stephen B. Dunbar Heather Rickels Keyu Chen ITP Research Series 2014.2 A Comparative
More informationAdjustment Factors in NSIP 1
Adjustment Factors in NSIP 1 David Notter and Daniel Brown Summary Multiplicative adjustment factors for effects of type of birth and rearing on weaning and postweaning lamb weights were systematically
More informationEXQUISITELY DESIGNED AQUARIUMS FOR ALL EXPERIENCE LEVELS.
EXQUISITELY DESIGNED AQUARIUMS FOR ALL EXPERIENCE LEVELS. Waterbox Aquariums Glass Overflow System Designed by a team of R&D professionals that have over 100 years combined experience in the aquatics industry.
More informationWhat is the average time needed to train a dog using a pet containment system?
Basic FAQs We hope that you will find the answers to your questions either in the FAQ section or in our Resource library. There is a lot of valuable information here, but it is worth reading all of it.
More informationYELLOW VIBRATION BARK COLLAR
YELLOW VIBRATION BARK COLLAR Congratulations on buying this Our K9 Bark Collar, if for any reason you are not 100% completely satisfied with your Bark Collar, please contact me immediately so that I may
More informationA Unique Approach to Managing the Problem of Antibiotic Resistance
A Unique Approach to Managing the Problem of Antibiotic Resistance By: Heather Storteboom and Sung-Chul Kim Department of Civil and Environmental Engineering Colorado State University A Quick Review The
More informationutca mother board for FMC ADC daughter cards
utca mother board for FMC ADC daughter cards Stefan Korolczuk National Centre for Nuclear Research, Otwock-Świerk, Poland Warsaw, 2011 S. Korolczuk (NCBJ) Fast EVM Warsaw 2011 1 / 17 Agenda 1 Introduction
More informationGARNET STATIC SHOCK BARK COLLAR
GARNET STATIC SHOCK BARK COLLAR Congratulations on buying this Our K9 Bark Collar, if for any reason you are not 100% completely satisfied with your Bark Collar, please contact me immediately so that I
More informationDog ecology studies oral vaccination of dogs Burden of rabies
Dog ecology studies oral vaccination of dogs Burden of rabies By F.X. Meslin WHO Geneva at the occasion of the intercountry Expert Workshop on Protecting Humans from Domestic and Wildlife Rabies in the
More informationIDR : VOL. 10, NO. 1, ( JANUARY-JUNE, 2012) : ISSN :
IDR : VOL. 10, NO. 1, ( JANUARY-JUNE, 2012) : 45-53 ISSN : 0972-9437 A STUDY ON PROBLEMS OF PRACTICING POULTRY FARMING IN NAMAKKAL DISTRICT E. P. Vijayakumar * & V. Ramamoorthy ** ABSTRACT Poultry farming
More information288 Seymour River Place North Vancouver, BC V7H 1W6
288 Seymour River Place North Vancouver, BC V7H 1W6 animationtoys@gmail.com February 20 th, 2005 Mr. Lucky One School of Engineering Science Simon Fraser University 8888 University Dr. Burnaby, BC V5A
More informationPet Selective Automated Food Dispenser
Pet Selective Automated Food Dispenser By Advika Battini Ali Yaqoob Vibhu Vanjari TA: Yuchen He Team Number: 46 Proposal for ECE 445, Senior Design, Spring 2018, University of Illinois Urbana Champaign
More informationFCI LT LM UNDERGROUND
FCI LT LM UNDERGROUND Faulted Circuit Indicator for Underground Applications Catalogue # s #29 6028 000 PPZ, #29 6015 000 PPZ, #29 6228 000, #29 6215 000 Description The Navigator LT LM (Load Tracking,
More informationUltra Min No-Bark Training Collar Ultra Small Ultra Powerful Ultra Control
No-Bark Dog Training Device Owner s Manual Ultra Min-e 2090 TM No-Bark Training Collar Ultra Ultra Ultra Small Powerful Control D.T. Systems, Inc. 1 Congratulations and thank you for purchasing our Ultra
More informationComplete Solutions for BROILER BREEDERS
Complete Solutions for BROILER BREEDERS Global Presence Local Commitment Feeding Drinking Climate Housing Complete Broiler Breeder Packages Broiler-Breeders We at Plasson are aware that the main goal in
More informationOur K9 LLC 616 Corporate Way Valley Cottage New York GARNET STATIC SHOCK BARK COLLAR USERS GUIDE
Our K9 LLC 616 Corporate Way Valley Cottage New York 10898 GARNET STATIC SHOCK BARK COLLAR USERS GUIDE STATIC SHOCK BARK COLLAR Congratulations on buying this Our K9 Bark Collar, if for any reason you
More informationDraft ESVAC Vision and Strategy
1 2 3 7 April 2016 EMA/326299/2015 Veterinary Medicines Division 4 5 6 Draft Agreed by the ESVAC network 29 March 2016 Adopted by ESVAC 31 March 2016 Start of public consultation 7 April 2016 End of consultation
More informationK9K-914 Anti Bark Collar User's Manual. Introduction:
K9K-914 Anti Bark Collar User's Manual Introduction: The k9konnection K9K-914 Anti-Bark Dog Collar stops barking with progressively increasing sound and shock which is controlled by a microprocessor distinguishing
More informationAnswers to Questions about Smarter Balanced 2017 Test Results. March 27, 2018
Answers to Questions about Smarter Balanced Test Results March 27, 2018 Smarter Balanced Assessment Consortium, 2018 Table of Contents Table of Contents...1 Background...2 Jurisdictions included in Studies...2
More informationHours of manual cash counting reduced to 12 minutes. John G. Shedd Aquarium, USA
Hours of manual cash counting reduced to 12 minutes John G. Shedd Aquarium, USA ABOUT JOHN G. SHEDD AQUARIUM Shedd Aquarium/Brenna Hernandez Glory s machines are a huge time-saver. I don t think we had
More informationNATURA CAGE-FREE. Modern aviary system for barn and free range egg production
NATURA CAGE-FREE Modern aviary system for barn and free range egg production NATURA aviary systems for layers: Flexible, efficient, user and bird friendly NATURA a well-established and proven system, which
More informationFREQUENTLY ASKED QUESTIONS Pet Owners
How does the Assisi Loop work? By emitting bursts of microcurrent electricity, the Assisi Loop creates a field which evenly penetrates both soft and hard body tissue around the target area. This electromagnetic
More informationHALE SECURITY PET DOOR CAT GUARDIAN patent pending
HALE SECURITY PET DOOR CAT GUARDIAN patent pending The Cat Guardian is an electronics package that can be added to a Hale Pet Door door or wall model of at least 1 3 / 8 thick to allow dogs free passage
More informationDemystifying Poultry Ventilation Ventilation 101
Demystifying Poultry Ventilation Ventilation 101 Western Poultry Conference - 2016 Why ventilate poultry barns? Oxygen for birds? Fresh air? Clearing out noxious gases? Temperature Regulation (Cooling
More informationGENETIC DRIFT Carol Beuchat PhD ( 2013)
GENETIC DRIFT Carol Beuchat PhD ( 2013) By now you should be very comfortable with the notion that for every gene location - a locus - an animal has two alleles, one that came from the sire and one from
More informationRESPONSIBLE ANTIMICROBIAL USE
RESPONSIBLE ANTIMICROBIAL USE IN THE CANADIAN CHICKEN AND TURKEY SECTORS VERSION 2.0 brought to you by: ANIMAL NUTRITION ASSOCIATION OF CANADA CANADIAN HATCHERY FEDERATION CANADIAN HATCHING EGG PRODUCERS
More informationSubdomain Entry Vocabulary Modules Evaluation
Subdomain Entry Vocabulary Modules Evaluation Technical Report Vivien Petras August 11, 2000 Abstract: Subdomain entry vocabulary modules represent a way to provide a more specialized retrieval vocabulary
More informationKeeping and Using Flock Records Scott P. Greiner, Ph.D. Extension Animal Scientist, Virginia Tech
Keeping and Using Flock Records Scott P. Greiner, Ph.D. Extension Animal Scientist, Virginia Tech Flock record-keeping is vital component of a successful sheep enterprise. Most often we associate the term
More informationK9 Pipeline Leak Detection
K9 Pipeline Leak Detection A NEW APPLICATION FOR A PROVEN TECHNOLOGY Utica Midstream June 2017 Outline Who we are Our dogs Why are dogs at a pipeline show? How does K9 leak detection work Responsive K9
More informationDefine evidence based practices for selection and duration of antibiotics to treat suspected or confirmed neonatal sepsis
GLOBAL AIM: Antibiotic Stewardship Perinatal Quality Improvement Teams (PQITs) will share strategies and lessons learned to develop potentially better practices and employ QI methodologies to establish
More informationof Conferences of OIE Regional Commissions organised since 1 June 2013 endorsed by the Assembly of the OIE on 29 May 2014
of Conferences of OIE Regional Commissions organised since 1 June 2013 endorsed by the Assembly of the OIE on 29 May 2014 2 12 th Conference of the OIE Regional Commission for the Middle East Amman (Jordan),
More informationICAO WCO Joint Conference on Enhancing Air Cargo Security and Facilitation
ICAO WCO Joint Conference on Enhancing Air Cargo Security and Facilitation IMPLEMENTATION OF MOST PROGRESSIVE METHODS OF USING DOGS FOR CARGO SCREENING Azat G. Zaripov, Deputy Head of Aviation Security
More informationCIT-COP Inf.5. Analysis of the Consultative Committee of Experts on the Compliance with the IAC Resolutions by the Party Countries
Analysis of the Consultative Committee of Experts on the Compliance with the IAC Resolutions by the Party Countries Report to the 6 th Conference of Parties This document takes into consideration the careful
More informationThe Kaggle Competitions: An Introduction to CAMCOS Fall 2015
The Kaggle Competitions: An Introduction to CAMCOS Fall 15 Guangliang Chen Math/Stats Colloquium San Jose State University August 6, 15 Outline Introduction to Kaggle Description of projects Summary Guangliang
More informationRicky Thaper Treasurer Poultry Federation of India Website:
Ricky Thaper Treasurer Poultry Federation of India Email: ricky@pfindia.org Website: www.pfindia.org Indian poultry industry is in growth mode. It has been growing at around 8-10% annually during the last
More informationOptimal Efficient Meta Heauristic Based Approch for Radial Distribution Network
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 4 Issue 7 July 2015 PP.65-69 Optimal Efficient Meta Heauristic Based Approch for Radial Distribution
More informationInformed search algorithms
Revised by Hankui Zhuo, March 12, 2018 Informed search algorithms Chapter 4 Chapter 4 1 Outline Best-first search A search Heuristics Hill-climbing Simulated annealing Genetic algorithms (briefly) Local
More informationICAO PUBLIC KEY DIRECTORY (ICAO PKD) 2007 ANNUAL REPORT TO PARTICIPANTS
PKD - WP/1 17/12/2007 ICAO PUBLIC KEY DIRECTORY (ICAO PKD) 2007 ANNUAL REPORT TO PARTICIPANTS Purpose 1. This annual report provides information on the operation of, and issues facing, the ICAO PKD. Background
More informationComments from The Pew Charitable Trusts re: Consultation on a draft global action plan to address antimicrobial resistance September 1, 2014
Comments from The Pew Charitable Trusts re: Consultation on a draft global action plan to address antimicrobial resistance September 1, 2014 The Pew Charitable Trusts is an independent, nonprofit organization
More informationLoose Leash Walking. Core Rules Applied:
Loose Leash Walking Many people try to take their dog out for a walk to exercise and at the same time expect them to walk perfectly on leash. Exercise and Loose Leash should be separated into 2 different
More informationKing Fahd University of Petroleum & Minerals College of Industrial Management
King Fahd University of Petroleum & Minerals College of Industrial Management CIM COOP PROGRAM POLICIES AND DELIVERABLES The CIM Cooperative Program (COOP) period is an essential and critical part of your
More informationBROOD REDUCTION IN THE CURVE-BILLED THRASHER By ROBERTE.RICKLEFS
Nov., 1965 505 BROOD REDUCTION IN THE CURVE-BILLED THRASHER By ROBERTE.RICKLEFS Lack ( 1954; 40-41) has pointed out that in species of birds which have asynchronous hatching, brood size may be adjusted
More informationFIF CAT WG Discussion Document Firm-Designated ID Walk-Through Originally Submitted: April 8, 2013, Updated August 5, 2014
FIF CAT WG Discussion Document Firm-Designated ID Walk-Through Originally Submitted: April 8, 2013, Updated August 5, 2014 This document is a consolidation of FIF comments submitted to the SROs on CAT
More informationMSc in Veterinary Education
MSc in Veterinary Education The LIVE Centre is a globally unique powerhouse for research and development in veterinary education. As its name suggests, its vision is a fundamental transformation of the
More information